In double data rate (DDR) dynamic random-access memory (DRAM) technology, ZQ calibration commands are used to periodically calibrate the DRAM drive strength and termination values. For example, a memory controller may generally issue the ZQ calibration commands to compensate any system voltage and temperature (VT) variations in the input/output (I/O) drivers associated with the DRAM. One ZQ calibration command used to calibrate the DRAM is referred to as a ZQ “long” command, which is often used during power-up initialization and during reset conditions. In addition, another ZQ calibration command is referred to as a ZQ “short” command, which tends to be used to track minor variations in voltage and temperature during normal operation and to periodically calibrate the DRAM while idle to maintain a linear output driver and termination impedance over a full voltage and temperature range. The ZQ short command takes one hundred twenty-eight (128) DRAM clock cycles to complete, whereas the ZQ long command takes a longer time to complete, typically five hundred twelve (512) DRAM clock cycles. However, the ZQ long command can compensate larger voltage and temperature deviations relative to the last time that the ZQ calibration was run.
DDR DRAM also supports various low-power modes, including a self-refresh mode in which the DRAM can issue internal refreshes to preserve data stored therein. Because the self-refresh mode has a low power consumption (e.g., relative to an auto-refresh where the memory controller pre-charges and then refreshes all open rows), the DRAM may be configured to automatically enter the self-refresh mode to save power when there is no memory traffic. Because the DRAM self-refresh mode may depend on whether there is memory traffic, the self-refresh mode may also be called traffic-based self-refresh. However, the DRAM cannot serve ZQ calibration commands while in the self-refresh mode. Accordingly, one challenge is to handle the interaction between the periodic ZQ calibration and the traffic-based self-refresh mode, as there may not be a need to calibrate the DRAM during self-refresh because there is no traffic. However, in the event that a memory rank spends substantial time in the self-refresh mode because the memory rank does not receive any traffic, larger voltage and temperature variations may accumulate while the memory rank stays in the self-refresh mode. In such cases, memory access timing may deteriorate and a ZQ calibration may be necessary before any traffic can resume. Furthermore, another concern in managing ZQ calibration is that the data input/output (DQ) bus shared among all dual in-line memory modules (DIMMs) in a DDR channel needs to be stable during ZQ calibration. Accordingly, ZQ calibration can stall the entire memory channel, blocking traffic to all ranks, whereby the performance impact that ZQ calibration will contribute may increase with more ranks in the memory system. For example, in a multi-rank system such as a channel with two (2) DIMMs, each rank may enter and exit self-refresh mode independently based on the incoming memory traffic. In such a multi-rank system, the periodic ZQ calibration must be issued to each rank, thus increasing complexity with respect to how the periodic ZQ commands interact with the self-refresh mode in each rank.
As such, because ZQ calibration can take considerable time and substantially impact memory latency due to stalling the entire memory channel, techniques to increase the time that memory ranks spend in self-refresh mode and reduce channel stall time are desired to improve memory power consumption and performance.